The present invention relates generally to insulated gate field effect transistors and more specifically to an improved high voltage insulated gate field effect transistor.
Many MOS applications require a device which can operate with a drain voltage much higher (for N channel device) or lower (for P channel device) than the source, body and gate voltages. In a conventional MOS structure, this requires long channels to avoid drain to source punch-through through the lightly doped body. It also requires thick gate oxide where the gate electrode overlaps the drain to avoid gate voltage induced field crowding at the drain body junction which reduces that junction's breakdown voltage. Both of these requirements degrade other characteristics of the device such as transconductance.
A known structure which alleviates these restrictions is the double diffused (DMOS) structure shown in FIG. 1. It uses a lightly doped drain into which body and source diffusions are made. In the conventional structure, the body and source portions adjacent the drain are self-aligned using a common mask edge. Channel length is thus the difference between lateral diffusion of the source and that of the body. Punch-through is avoided by allowing the drain-body depletion layer to spread primarily into the drain which is more lightly doped than the body. The gate overlaps only the lightly doped part of the drain where it acts as a field plate which tends to increase drain-body junction breakdown. Thus, the double diffused structure alleviates the problems of the conventional MOS when high voltage is required.
The double diffused structure has several disadvantages. One is a result of the source-body self alignment. For low threshold voltage V.sub.T, the maximum channel surface doping must be low. For high drain-source voltage, the total doping under the source must be high to suppress punch through. However, the doping under the source is essentially the same as the body doping due to the self-alignment of body and source. The result is that channel surface doping can be held low while total body doping is held high only if channel length is made long, thus compromising one of the structure features. Threshold adjustment implants might be used to alleviate the problem, but they add cost and are difficult to control when subjected to the relatively long diffusion cycle of the body which is done after the gate electrode is patterned.
Thus, it is an object of the present invention to provide a high voltage MOS structure which is capable of having low threshold voltages.
Another object of the present invention is to provide a high voltage, low threshold MOS structure without requiring additional processing steps.
Still another object of the present invention is to provide a method of fabricating a high voltage MOS structure with a range of selectable threshold voltages on a single integrated circuit without modifying the process sequence.
A further object of the present invention is to provide a high voltage, low threshold voltage, vertical MOS device.
These and other objects of the invention are attained by selectively forming the source region of a double diffused MOS device in the decreasing impurity portion of a diffused body to set the peak impurity concentration in the channel region of the diffused body to the peak impurity concentration required for specific device threshold voltage. Thus, for a given body and source impurity introduction steps, the threshold of the device can be varied by the mere location of the source region relative to the decreasing impurity concentration of the body region. A high threshold device may also be formed by forming its source region in the substantially constant impurity concentration region of its body region. For a vertical MOS device, the body region is formed as an annulus and the channel region is adjacent the interior of the annulus. A body contact region is adjacent the outer edge of the body annulus and a drain contact is provided either on the bottom of the substrate or at a top surface adjacent the outer edge of the body region. The spacing of the bottom edge of the source region to the bottom edge of the body region is substantially greater than the distance between the side edge of the source region and the inner side of the body region.
Serially connected, merged, insulated gate field effect transistors may be formed wherein one of the field effect transistors has substantially lower threshold voltage than the other and preferably is a depletion device. This includes a common body region having first and second source/drain regions formed therein wherein the first source/drain region is of the lower threshold device and is formed in the decreasing impurity concentration region of the body and the second source/drain region is formed in the constant impurity concentration region. A first gate is formed over the decreasing impurity body region between the first source/drain regions and the substrate, and a second gate region is formed over the body region of constant impurity concentration separating the first and second source/drain regions. Drain contact is made to the substrate adjacent the first gate region. The first gate may be connected to the first source/drain region and the second source/drain region may have a contact connected directly to the body region.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.